Processing of Fluxing Underfills for Flip Chip-on-Laminate Assembly

Presented at APEX 2002, San Diego, CA

Renzhe Zhao & R. Wayne Johnson
Laboratory for Electronics Assembly & Packaging - Auburn University
162 Broun Hall, ECE Dept.
Auburn, AL 36489
334-844-1880
johnson@eng.auburn.edu
Greg Jones
KIC
15950 Bernardo Center Dr. #E
San Diego, CA 92127
775-322-0158
DrJ@kicmail.com
Erin Yaeger, Mark Konarski, Paul Krug & Larry Crane
Loctite Corporation
1001 Trout Brook Crossing
Rocky Hill, CT 06067
860-571-5497
larry.crane@loctite.com

Fluxing underfill eliminates process steps in the assembly of flip chip-on-laminate (FCOL) when compared to conventional capillary flow underfill processing. In the fluxing underfill process, the underfill is dispensed onto the board prior to die placement. During placement, the underfill flows in a 'squeeze flow' process until the solder balls contact the pads on the board. The material properties, the dispense pattern, and resulting shape, placement force, placement speed, and hold time all impact the placement process and the potential for void formation. A design of experiments was used to optimize the placement process to minimize placement-induced voids. The major factors were identified were placement force and placement acceleration.

During the reflow cycle, the fluxing underfill provides the fluxing action required for good wetting and then cures by the end of the reflow cycle. With small, homogeneous circuit boards it is relatively easy to develop a reflow profile to achieve good solder wetting. However, with complex SMT assemblies involving components with significant thermal mass this is more challenging. To get the large thermal mass components to temperature, the small flip chip die will be at higher temperatures for longer periods of time. Use of predictive software tools to optimize the reflow profile and minimize temperature differences across the board is required. A series of experiments were performed using these tools to optimize the reflow profile of a complex FCOL/SMT assembly. The profile obtained was used to successfully assembly flip chip die with fluxing underfill.


Flip chip on laminate (FCOL) provides advantages in size, weight and performance for portable products. However, the industry has been slow in adopting FCOL technology. One issue often sited is the equipment and time associated with capillary underfill dispense, flow and cure. Fast flow, snap cure underfills are one solution to decreasing dispense, flow and cure times in a high volume production environment.

An alternate approach is to use fluxing underfills.[1,2] Fluxing underfills are polymer systems that incorporate fluxing activity into an underfill. Prior to assembly, the boards must be dehydrated to remove absorbed moisture and to ensure the solder mask has been fully cured. Moisture and volatiles from under cured solder mask can cause bubbles (voids) in the fluxing underfill during the reflow temperature cycle.

The fluxing underfill is dispensed onto the dehydrated PWB at the flip chip site and the die is placed through the fluxing underfill. During placement, the underfill flows in a 'squeeze flow' process until the solder balls contact the pads on the board. Ideally, the fluxing underfill will make initial contact with the center of the die and flow radially outward as the die is placed. This would happen if the bottom of the flip chip were a flat plate as is usually assumed in squeeze flow models. However, flip chip die have solder balls that interfere with the ideal flow pattern. Voids (trapped air) can be created in the underfill near the solder balls during placement. The viscosity, surface tension and wetting characteristics of the underfill along with the placement parameters of force, acceleration (velocity) and hold time affect the formation of these placement voids. The optimization of placement parameters through a design of experiments is discussed in a later section.

The assembly is then sent through reflow oven. The fluxing underfill provides the necessary fluxing activity for good solder wetting. Depending on the cure kinetics, the underfill may cure during the reflow cycle or a post reflow cure may be required.

The reflow profile and cure kinetics are important for high yield assembly. As the underfill temperature increases during the reflow cycle, the viscosity of the underfill decreases. However, as cure is initiated the viscosity of the underfill will increase. When the solder melts and begins to wet to the substrate metallization, the viscosity of the underfill must be low enough to allow collapse of the chip. Failure of the chip to collapse will result in poor or open solder joints.

With small, homogeneous circuit boards it is relatively easy to develop a reflow profile to achieve good solder wetting. However, with complex SMT assemblies involving components with significant thermal mass this is more challenging. To get the large thermal mass components to temperature, the small flip chip die will be at higher temperatures for longer periods of time. Use of predictive software tools to optimize the reflow profile and minimize temperature differences across the board is required. A series of experiments were performed using these tools to optimize the reflow profile of a complex FCOL/SMT assembly. The details are presented in a later section.

For the reflow profile studies the test board shown in Figure 1 was used. The board is 4.0" x 6.0" x 0.060". The components assembled onto the board are listed in Table 1.

Figure 1: Photograph of Test Vehicle Used in Reflow Profile Experiments
Figure 1: Photograph of Test Vehicle Used in Reflow Profile Experiments

Table 1: Components on Test Vehicle (Figure 1)

Description Pitch Ball Diameter Length x Width Height Reference Designators
PBGA 352 I/O 0.050" (1.27mm) .030" (.75mm) 1.38" SQ .090" u201
CBGA 360 I/O 0.050" (1.27mm) .035" (.89mm) .983" SQ .200" u204
Column Grid Array 360 I/O 0.050" (1.27mm) column .035 dia x .065 tall .983" SQ .120" u204
Flex PBGA 144 I/O (uBGA) 0.033" (.80mm) .020" (.5mm) .473" SQ .043" u205 - u208,u230,u231
DCA 96 I/O (flipchip) .017" (.45mm) .008" (.19mm) .500" SQ .030" u261, u262
DCA 48 I/O (flipchip) .017" (.45mm) .008" (.19mm) .250" SQ .030" u232, u233
Tape array BGA 96 I/O (CSP) .020" (.5mm) .012" (.3mm) .317" SQ .038" u251, u252
uBGA 46 I/O .030" (.75mm) .012" (.3mm) .223" x .305" .033" u237 - u242
uBGA 48 I/O .030" (.75mm) .020" (.5mm) .197" x .324" .030" u211 - u214, u218, u220
Mini BGA 48 I/O .030" (.75mm) .012" (.3mm) .275" SQ .044" u217, u219

A PB-8 2x2 test board was used for the placement optimization study. The PB-8 2x2 die is 0.200" x 0.200" and has solder balls on 0.008" pitch. The test board has 10 die sites. The die sites were designed using a finger pattern as shown in Figure 2. The finger board design was chosen to improve the squeeze flow of the underfill during the placement of the die. The solder mask pattern is less likely to trap air voids.

Loctite FMD 806 fluxing underfill was used for the process development. This underfill cures during the reflow cycle, eliminating the need for a post reflow cure.

Figure 2: Photograph of Finger Board Design
 
Figure 2: Photograph of Finger Board Design
Figure 2: Photograph of Finger Board Design

The reflow profile experiments were performed in a Heller 1800 reflow oven with 9 zones. For the profile development, a SlimKIC 2000 profiling system was used. This automated prediction tool allows users to predict how changes to belt speed and oven set points will affect a product profile. The software option can create and evaluate billions of potential oven recipes, automatically selecting the recipe that best fits the process window in about a minute. The automated predictive tool is designed to center the profile in a process window designated by the user, who may set limits particular to their processes.

For the initial profile development, a maximum ramp rate, soak time between 140°C and 155°C, time above 183°C, and peak temperature were input into the software based on the fluxing underfill processing recommendations. An initial profile was set into the reflow oven based on past flip chip reflow experience. Thermocouples were located underneath components U261 (flip chip), U207 (flex PBGA), U201 (PBGA), U204 (CCGA), U252 (TABGA), U237 (uBGA), and U219 (mini BGA). Figure 3 shows the results of the initial profile.

Figure 3: Initial Reflow Profile
Figure 3: Initial Reflow Profile

The profile for the flip chip die was within an acceptable range. However, as expected, the ceramic column grid array profile was on the low end and marginal. The peak temperature was 208.8°C (11.3°C cooler than the flip chip). The soak time for the CCGA was only 37 seconds and the time above 183°C was 65.7 seconds.

The software identified the CCGA as not within specifications and provided recommendations for new oven set points. Following an iterative process of profiling and following refined recommendations from the software a profile was quickly achieved with nearly equal soak times and times above 183°C for all components. The difference in peak temperature between the flip chip and the CCGA was 9.4°C, an acceptable difference. The profile is shown in Figure 4.

Figure 4: Optimized Reflow Profile Based on Initial User Inputs
Figure 4: Optimized Reflow Profile Based on Initial User Inputs

Flip chip die were assembled and reflowed using this profile. The electrical assembly yield was 0%. Figure 5 shows a cross section of one of the die. There is no wetting of the solder top the copper pad. This indicates the fluxing underfill had cross-linked and its viscosity increased sufficiently prior to melting of the solder balls to prevent collapse.

Figure 5: Cross-section Showing No Solder Wetting with the Profile in Figure 4
Figure 5: Cross-section Showing No Solder Wetting with the Profile in Figure 4

In reviewing the two profiles, the 'optimized' profile is approximately 100 seconds longer than the original profile. This additional time prior to melting of the solder was sufficient for significant cross-linking of the underfill. In the profile optimization, no constraint was placed on profile length.

The software allows time constraints, so a time constraint of 180-200 seconds above 140°C was added. As determined by DSC, the onset temperature for underfill curing is 150-160°C. The profile iteration was repeated with the additional constraint and the profile shown in Figure 6 was obtained. The soak time for all components was approximately the same and the time above 183°C was only about 10 seconds less for the CCGA. The peak temperature difference between the CCGA and the flip chip die was less than 8°C (223.4°C vs. 215.5°C).

Figure 6: Final Reflow Profile
Figure 6: Final Reflow Profile

Figure 7 is a cross-section of a flip chip solder joint reflowed with the final profile. Excellent wetting of the copper trace is observed.

Figure 7: Cross-section of Flip Chip Solder Joint Obtained with Final Reflow Profile
Figure 7: Cross-section of Flip Chip Solder Joint Obtained with Final Reflow Profile

A Camalot 3700 dispense system, a Siemens F5 pick & place system and a Heller 1800 reflow oven were used in the placement optimization study. The experiment was designed using Taguchi's parameter design (PDE) method. The PDE is based on classical fractional factorial designs. In the factorial design, the effects of the experimental noise factors are averaged out over all treatment combinations (TCs) through randomization. Unlike the factorial designs, Taguchi's method imbeds the noise factors in the design of the experiment so that randomization is generally unnecessary. Experimental noise factor is defined as those variables that are either too difficult or too expensive to control in Taguchi's parameter design. For example, environmental conditions, deterioration of parts, material and subcomponents, and piece-to-piece variation belong to noise factors. Based on Taguchi's parameter design, optimal factor levels can be selected in order to make the product more robust against noise.

In a previous experiment[3], four controllable factors, underfill volume, placement acceleration, placement force and placement dwell time, were studied by Taguchi's design of L9(34). Placement acceleration and placement force were identified as important parameters, and underfill volume and placement dwell time were less important parameters.

In this experiment, the objective was to refine the parameter range selected based on the previous results. The interaction between placement force and placement dwell time was also studied. Taguchi's L9(34) design was used. There were three controllable factors, placement acceleration, placement force and placement dwell time. Each of these has three levels as shown in Table 2. Placement site (die site) was taken as a noise factor. It has four levels, referring to samples 1 to 4. The response variables are assembly yield and placement underfill voids. The design layout is shown in Table 3. In the table, AxB is the interaction between variables A and B.

Table 2: Controllable Factors

Controllable Factor Level 1 Level 2 Level 3
A: Placement Force 1N 3N 5N
B: Placement Dwell Time 0s 1.5s 3s
C: Placement Acceleration 0.1g 1.3g 2.6g

Table 3: The Design Layout

Run No. DOE factors
A B AxB C
1 1 1 1 1
2 1 2 2 2
3 1 3 3 3
4 2 1 2 3
5 2 2 3 1
6 2 3 1 2
7 3 1 3 2
8 3 2 1 3
9 3 3 2 1

The PB8 2x2 test vehicle was used in the experiment and the PWBs were dehydrated at 125°C for 24 hours before assembly. Quartz die were used initially to verify that voids observed after reflow were due to placement and not outgassing or moisture generated/liberated during the reflow profile. The underfill volume used was 0.006ml. A single dot was dispensed in the center of the die site. The reflow profile used matched the final profile developed in the reflow profile development study.

The assembly yield was 100% yield for all placement conditions. That means the factors at current levels do not affect the assembly yield.

Table 4: The Experimental Results

Run No. DOE Factors Samples (Voids) ndb
A B AxB C 1 2 3 4
1 1 1 1 1 8 4 9 5 -16.67
2 1 2 2 2 7 13 9 11 -20.21
3 1 3 3 3 10 3 7 1 -15.99
4 2 1 2 3 2 1 2 1 -3.98
5 2 2 3 1 2 1 0 7 -11.30
6 2 3 1 2 3 3 5 4 -11.69
7 3 1 3 2 3 2 0 4 -8.60
8 3 2 1 3 3 0 0 2 -5.12
9 3 3 2 1 1 2 2 2 -5.12

Figure 8: Example of Placement Voids Seen in a Polished Flat-section
Figure 8: Example of Placement Voids Seen in a Polished Flat-section

To examine the die for placement voids, both C-SAM images and flat-sections (polish the die away) were examined. Since the voids were near the edge of the die, flat-sectioning provided a better method for identifying and counting voids. Figure 8 shows an example of a placement void. Table 4 shows the results for the response variable, underfill placement voids. Because less underfill voiding is desired, the design type is smaller-the-better (STB). According to Taguchi's design, the signal to noise (S/N) ratio, ndb, for STB was calculated with this equation:

Taguchi's design - equation

where, n is the total number of samples and yi is the value for response variable. In our case, yi is the number of underfill voids and n = 4. Table 4 gives the ndb.

The response table (RT) and the ANOVA table for S/N ratio is shown in Table 5. From Table 5, variable A (placement force) is a strong factor, variable C (placement acceleration) is a moderate factor, and B (placement dwell time) is weak factor. The interaction between A and B is not significant.

Table 5: Response and ANOVA Results

RT A B AxB C
L1 -52.88 -29.26 -33.48 -33.10
L2 -26.97 -36.63 -29.31 -40.50
L3 -18.84 -32.80 -35.90 -25.09
df 2 2 2 2
SS 210.67 9.07 7.41 39.61
MS 105.33 4.54 3.70 19.80
Ri 1 3 4 2

Based on the response table, the optimal parameter level for voids reduction is A3B1C3. In other words, the optimal combination is placement force at level 3 (5N), placement dwell time at level 1 (0s), and placement acceleration at level 3 (2.6g).

After determining the optimal parameter combination, experiments were conducted to verify the best condition. Figure 9 shows that void-free assembly was achieved with the optimized parameters. The assembly yield was 100% and the excellent solder wetting is shown in Figure 10.

Figure 9: Void Free Assembly with Optimized Placement Parameters
 
Figure 9: Void Free Assembly with Optimized Placement Parameters
Figure 9: Void Free Assembly with
Optimized Placement Parameters

Figure 10: Cross-section Showing Excellent Wetting with Optimized Assembly Process
Figure 10: Cross-section Showing Excellent Wetting
with Optimized Assembly Process

Fluxing underfills offer an alternative to capillary flow underfills in the assembly of flip chip on laminate. Successful assembly requires development of optimized placement parameters to eliminate placement-induced voids. The parameters will be a function of the specific die and underfill used.

The reflow profile can be optimized using predictive software for complex PWBs with a wide range of component sizes and thermal masses. Care must be used to establish the proper constraints for the software.

  1. Doug Katze, "No-Flow Fluxing Underfill Process Characterization," Proceedings of the 2001 APEX Conference, San Diego, CA, January 14‑18 2001, pp. MT2-2 1 to MT2-2 9.
  2. Michael A. Previti, "No-Flow Underfill: A Reliability and Failure Mode Analysis," Proceedings of the 2001 APEX Conference, San Diego, CA, January 14‑18 2001, pp. MT2-1 1 to MT2-1 5.
  3. Renzhe Zhao, Prasanna Kulkarni, Yun Zhang, R. Wayne Johnson, Paul Krug, Erin Yaeger and Larry Crane, "Assembly with Fluxing Underfills: Modeling and Experimentation," presented at the IMAPS Topical Workshop on Flip Chip Technology, Austin, TX, June 18‑20 2001.

The authors would like to recognize Siemens Dematic, Speedline Camalot and Heller Industries for providing equipment used in this research.


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